Large scale integrated circuits, such as, for example, DRAM (dynamic random access memory) memory chips or logic chips, constitute complex three-dimensional arrangements in a semiconductor substrate which are fabricated in a plurality of patterning planes. A patterning plane comprises a lithographic imaging of structures predefined on a mask onto the semiconductor substrate to be patterned and subsequent etching, deposition or growth and planarization steps.
In a patterning plane, the structures are often established as lines and trenches in the semiconductor substrate which may be arranged periodically in dense fashion and insulated or semi-insulated and also have different lengths and widths. These different structures are imaged from the mask onto a photosensitive layer, provided on the semiconductor wafer, by an exposure step.
FIG. 1 shows a simplified illustration of a detail from a circuit layout 3 or a pattern to be formed on a semiconductor wafer and has both narrow, periodic, and densely arranged structures 33 and wide structures 35 and structures 31, 32, 34 arranged in insulated or semi-insulated fashion. Areas depicted dark in the illustration represent lines, i.e., elevated structure elements, in other words non-etched areas, on the semiconductor wafer.
The insulated contact structure 32 corresponds, for example, to a contact hole on the semiconductor wafer, which may be fabricated by irradiation of a corresponding light-transmissive section in the mask into a photosensitive layer on the semiconductor wafer (positive resist), subsequent development and transfer into an underlying layer in an etching step.
The structures contained in the circuit layout differ not only with regard to their length and width, but also with regard to their surroundings. In a real imaging process, insulated or semi-insulated structures are imaged differently than periodically arranged structures in the case of which an individual structure is situated in the vicinity of other structures. Periodically and densely arranged, narrow structures having dimensions close to the resolution limit of the imaging apparatus are imaged with a different quality than wide structures having dimensions further above the resolution limit of the imaging apparatus and/or insulated structures.
In order that the structures contained in the circuit layout described are transferred onto the semiconductor wafer, a mask layout is designed for a mask for a photolithographic imaging of structures on the mask onto the semiconductor wafer.
One example of a mask layout to be assigned to the circuit layout described and account for the different imaging behavior of different structures is illustrated in FIG. 2. Narrow structures 2 that are arranged densely in the circuit layout with critical dimensions with regard to the resolution capability of the imaging apparatus are embodied using CPL (chromeless phase edge lithography) technology. In this case, the structures 2 are etched as trenches 24 into the planar surface 71 of a transparent mask substrate 7 with a depth in the case of which a light beam transmitted by the mask substrate 7 through a trench 24 has a phase shift by half a wavelength relative to a light beam transmitted by the mask substrate 7 through the planar surface 71.
The structure formation on the semiconductor wafer is effected, inter alia, due to destructive interference of light beams that traverse the transparent mask substrate 7 in the region of the trench edges. In this case, the trenches 24 are made narrow so that two adjacent trench edges lead to a line formation in the resist in the semiconductor wafer. The lines are superimposed in terms of their sidewalls and thus merge to form a common line. Wide structures are formed in accordance with the mask layout 12 using HTPSM (half tone phase shifting mask) technology. In this technology, the structures are realized by semitransparent, phase-shifting sections 22 with a transmission of, for example, 6% and transparent sections 23. For periodizing structures 31, 32, 34 that are insulated and semi-insulated in the circuit layout 3, SRAF (subresolution assist features) structures 22a are provided as semitransparent, phase-shifting or transparent sections 22, 23 in the mask layout 12. The sections improve the imaging quality, essentially the depth of field, of the structures 2 and, since they are provided with dimensions below the resolution limit of the optical system, they are not concomitantly imaged onto the semiconductor wafer.
FIG. 2 illustrates the transparent mask substrate 7 with the trenches 24. The semi-insulated trench 24 is periodized by the SRAF structures 22a comprising semitransparent, phase-shifting material shown. The figure illustrates the semitransparent, phase-shifting sections 22 and the transparent sections 23, with which structures having less critical dimensions with regard to the resolution capability of the imaging apparatus are imaged onto the semiconductor wafer. The transparent section 23, which is surrounded by phase-shifting sections 22, is periodized by SRAF structures 22a that are likewise embodied as transparent sections 22. The dashed lines illustrated in the figure specify the lengths and widths of the structures 2 on the semiconductor wafer. In order to compensate for the line shortening effect that occurs during imaging, the structures in the mask layout are provided with adapted dimensions.
In order to fabricate a mask with the mask layout described in FIG. 2, the phase-shifting, semitransparent sections and the trenches are conventionally patterned in separate mask lithography steps.
FIG. 3 illustrates a mask blank 11 with a transparent mask substrate 7 with a planar surface 71. A semitransparent, phase-shifting layer 52 is provided on the surface 71. A light-absorbing absorber layer 51 is provided on the phase-shifting layer 52 and a photosensitive first resist layer 61 is provided on the absorber layer 51.
In a first mask lithography step, the layout for structures that are formed as semitransparent phase-shifting and transparent sections on the mask is imaged onto the resist layer, e.g., by an electron beam writer. After developing the resist layer, he structures are transferred into the absorber layer and the underlying semitransparent phase-shifting layer by means of an etching step.
For patterning the trenches in the transparent mask substrate, a new resist layer is applied, which is patterned in a second mask lithography step. The layout for the trenches is transferred into the resist layer, for example, by an electron beam writer. A subsequent development of the resist layer opens those regions of the resist layer at which trenches are intended to be etched into the transparent mask substrate. After the patterning of the resist layer, the trenches are etched into the mask substrate. The resist layer is then removed and, in order to form the phase-shifting sections, the patterned absorber layer is removed in a further etching step, so that the structures are formed by the patterned phase-shifting layer.
FIGS. 4A, 4B, and 4C show the mask 1 after three different stages of processing. FIG. 4A illustrates the mask 1 after the transfer of the structures formed as semitransparent, phase-shifting sections 22 and transparent sections 23. The patterned absorber layer 51, which forms opaque sections 21 on the transparent mask substrate 7, can be seen. The new resist layer 6 patterned in a second mask lithography step can be discerned in FIG. 4B. The resist layer 6 has openings through which trenches 24 etched into the mask substrate 7 are visible. After the trenches 24 have been etched into the mask substrate 7, the resist layer 6 is removed. FIG. 4C illustrates the mask 1 after the removal of the resist layer 6 and the absorber layer 51. The mask substrate 7, the trenches 24 etched into the mask substrate 7, the SRAF structures 22a, which are formed as semitransparent, phase-shifting sections 22, and the semitransparent, phase-shifting sections 22 that emerge from the patterned semitransparent phase-shifting layer 52 can be seen. The transparent sections 23 illustrated and also the transparent SRAF structures 22a emerge from the patterned phase-shifting layer 52 as openings at which the transparent mask substrate 7 becomes visible.
The conventional fabrication method described gives rise to a positional error with respect to one another among the structures produced by the different technologies, since the different structures are fabricated in two different mask lithography steps on the mask. The structures etched as trenches into the mask substrate have to be aligned with the structures formed as initially opaque sections. Since this can be done only with a limited alignment accuracy, an overlay error always arises and, under certain circumstances, again nullifies the advantage of the mask with differently formed structures. A further difficulty in the case of the mask fabrication described arises during the etching of the trenches into the mask substrate, in the case of which the patterned resist layer is used as an etching mask. Due to fluctuations in the resist profile in connection with resist removal, this leads to dimensional losses and feature size fluctuations on the mask.
In order to fabricate a mask with MESA-CPL structures, instead of the trench-CPL structures, a method analogous to the fabrication of the mask with trench-CPL structures is employed. MESA-CPL structures are understood here to be structures that are formed as transparent elevations in the mask substrate. In order to form suitable elevations, the mask substrate is partially etched back, thus resulting in depressions. The height difference is chosen such that a light beam that passes through the mask substrate through the non-etched surface at the elevations has a phase shift by half a wavelength relative to a light beam that passes through the mask substrate through the depression. The imaging on the semiconductor wafer is based on the same principle as in the case of the trench-CPL structures.
The conventional method for fabricating the mask with MESA-CPL structures and with structures that are formed by semitransparent, phase-shifting or opaque and transparent sections has, in accordance with FIGS. 5A-5C, in part the same process steps as the method already described.
FIGS. 5A, 5B, and 5C illustrate the mask with MESA-CPL structures in three different stages of processing. FIG. 5A shows the mask 1 after the first mask lithography, in the course of which the absorber layer 51 is patterned. FIG. 5A does not differ from FIG. 4A. The structures that are later formed as semitransparent, phase-shifting and transparent sections 22, 23 are transferred onto the mask 1 by the first lithography step. Afterward, a further resist layer 6 is applied and patterned by a second lithography step 5. This opens the resist layer 6 at the locations at which the mask substrate 7 is etched back. The resist layer 6 remains as an etching mask at the locations at which elevations 25 are formed. The resist layer 6 furthermore continues to cover regions in which the structures are formed as semitransparent phase-shifting or opaque and transparent sections 22, 21, 23. FIG. 5B illustrates the mask 1 with the patterned resist layer 6 after the depressions 26 have been etched into the mask substrate 7. The SRAF structures 22a formed as initially opaque sections 21 and the patterned absorber layer 51 can furthermore been seen. After the etching of the depressions 26, the resist layer 6 is removed and then the absorber layer 51 is removed. FIG. 5C illustrates the mask after the removal of the absorber layer 51 and the resist layer 6. FIG. 5C differs from FIG. 4C in that, instead of the trenches 24, elevations 25 are formed in the mask substrate 7.
The fabrication of the mask with MESA-CPL structures gives rise to the same difficulties as in the fabrication of the mask with trench-CPL structures. In the second mask lithography, the structures formed as elevations are aligned with the structures formed as phase-shifting sections. An overlay error occurs since the mask, after the first mask lithography, is removed from the mask writer and etched and cleaned and newly coated with resist and the resist is patterned. In this case, the second lithography plane is produced with the device-specific, limited alignment accuracy with respect to the first lithography plane.
In the case of the mask with MESA-CPL structures, too, resist structures serve as an etching mask for etching the depressions into the mask substrate. Dimensional losses and feature size fluctuations on the mask may likewise occur in this case, on account for example of fluctuations in the resist profile in connection with a resist removal.
A method for fabricating a mask having different types of structures by which a type of structures formed as trenches in the mask substrate can be positioned in a self-aligning manner, i.e., without positional errors, with respect to a type of structures formed as semitransparent, phase-shifting or opaque sections on the mask. A mask fabricated by the method are desirable. Further, a method for fabricating a mask in which elevations, instead of the trenches, elevations are formed in the mask substrate, and the mask fabricated by the method are desirable.